The present invention relates to a semiconductor device, as exemplified by a semiconductor device provided with a cache memory.
In recent years, a cache memory is employed in order to improve efficiency of a micro-processor system. A small-capacity instruction cache of a fully associative system is mounted in many cases, from a standpoint of a trade-off between an area and performance.
For example, a cache memory disclosed by Patent Literature 1 (Published Japanese Unexamined Patent Application No. 2000-339222) includes a hit/miss counter circuit (300) which holds the number of continuous occurrences of a cache hit or a cache miss corresponding to each entry, and a write control circuit (400) which controls whether to forbid replacement of an entry of a cache memory. In the write control circuit (400), the number of continuous hits as a condition for forbidding replacement and the number of continuous misses as a condition for canceling the forbidding replacement are set up, and whether the replacement is forbidden or not is controlled based on these conditions.